Freescale Semiconductor /MK24F12 /UART2 /C5

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Interpret as C5

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)LBKDDMAS 0 (0)ILDMAS 0 (0)RDMAS 0 (0)TCDMAS 0 (0)TDMAS

TCDMAS=0, RDMAS=0, TDMAS=0, LBKDDMAS=0, ILDMAS=0

Description

UART Control Register 5

Fields

LBKDDMAS

LIN Break Detect DMA Select Bit

0 (0): If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is asserted to request an interrupt service.

1 (1): If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is asserted to request a DMA transfer.

ILDMAS

Idle Line DMA Select

0 (0): If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is asserted to request an interrupt service.

1 (1): If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is asserted to request a DMA transfer.

RDMAS

Receiver Full DMA Select

0 (0): If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.

1 (1): If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.

TCDMAS

Transmission Complete DMA Select

0 (0): If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request signal is asserted to request an interrupt service.

1 (1): If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request signal is asserted to request a DMA transfer.

TDMAS

Transmitter DMA Select

0 (0): If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.

1 (1): If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.

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